The present invention relates to a microcontroller and an electronic control device using the same and, more particularly, to a technique which can be suitably used for a reliable electronic control device capable of continuing operation even when a failure occurs.
Automation of control is advancing and demand for safety and reliability of an electronic control device is increasing. To assure safety, an electronic control device is demanded to immediately detect abnormality at the time of occurrence of the abnormality and stop the operation. With respect to a processor processing information, to immediately detect abnormality at the time of occurrence of the abnormality and stop the operation, a method of providing two processors and comparing outputs of the two processors has been used from a long time ago. In recent years, as semiconductor processes are becoming finer, a plurality of processors can be mounted on one chip, and a safety microcontroller having in-chip redundancy that a memory necessary for the operation of the dual processors is added to the one chip is practically used mainly for vehicle control.
In recent years, it is demanded not only to immediately detect abnormality at the time of occurrence of the abnormality and stop the operation but also to continue the operation even at the time of a failure.
As the technical trend in recent years, the semiconductor processes are becoming finer and more processors can be mounted on one chip. Processors of the number necessary to continue operation even at the time of a failure can be mounted on one chip. To continue operation even at the time of a failure by simply applying the above-described technique, two sets of safety microcontrollers each configured by dual processors and a memory are mounted on one chip.
On the other hand, as a countermeasure against a failure in a memory, an error correction code (ECC) is applied. For example, an SECDED (Single Error Correction Double Error Correction) code is used. The code, as the name indicates, is suitable to a system in which when an error of one bit occurs, the error is corrected and the operation can be continued and, when an error of two bits occurs, the operation is stopped for the first time.
Patent literature 1 discloses a memory system realizing a sophisticated error correction only by a single general memory module. The system has “m” pieces of semiconductor memory chips having n-bit input and output. An error correction code of n bits×(m−l) is added to data of n bits×l, and n bits are stored in each of the m pieces of semiconductor memories (l, m, and n are natural numbers). As error correction capability, an error which occurs in one place in n-bit unit can be corrected and errors which occur in two places can be detected.